I am trying to run the below XML file using McPAT simulator to get power results, but I got a "Floating point exception (core dumped)" error. The XML file represents the out put of a gem5 model after converting it to XML form using a python parser file. i have a ubuntu 20.04 OS and McPAT (version 1.3 of Feb, 2015)
<!-- Number of Windows switches (number of function calls and returns)--> <!-- Alu stats by default, the processor has one FPU that includes the divider and multiplier. The fpu accesses should include accesses to multiplier and divider --> <stat name="ialu_accesses" value="stats.system.cpu.op_class_0::IntAlu + stats.system.cpu.op_class_0::IntDiv" /> <stat name="fpu_accesses" value="stats.system.cpu.op_class_0::FloatAdd + stats.system.cpu.op_class_0::FloatCmp + stats.system.cpu.op_class_0::FloatCvt + stats.system.cpu.op_class_0::FloatMult + stats.system.cpu.op_class_0::FloatMultAcc + stats.system.cpu.op_class_0::FloatDiv + stats.system.cpu.op_class_0::FloatMisc + stats.system.cpu.op_class_0::FloatSqrt + stats.system.cpu.op_class_0::SimdFloatAdd + stats.system.cpu.op_class_0::SimdFloatCmp + stats.system.cpu.op_class_0::SimdFloatCvt + stats.system.cpu.op_class_0::SimdFloatMult + stats.system.cpu.op_class_0::SimdFloatMultAcc + stats.system.cpu.op_class_0::SimdFloatDiv + stats.system.cpu.op_class_0::SimdFloatMisc + stats.system.cpu.op_class_0::SimdFloatSqrt + stats.system.cpu.op_class_0::SimdFloatAlu + stats.system.cpu.op_class_0::SimdFloatReduceAdd + stats.system.cpu.op_class_0::SimdFloatReduceCmp" /> <stat name="mul_accesses" value="stats.system.cpu.op_class_0::IntMult" /> <stat name="cdb_alu_accesses" value="0" /> <stat name="cdb_mul_accesses" value="0" /> <stat name="cdb_fpu_accesses" value="0" /> <!-- multiple cycle accesses should be counted multiple times, otherwise, McPAT can use internal counter for different floating point instructions to get final accesses. But that needs detailed info for floating point inst mix --> <!-- currently the performance simulator should make sure all the numbers are final numbers, including the explicit read/write accesses, and the implicit accesses such as replacements and etc. Future versions of McPAT may be able to reason the implicit access based on param and stats of last level cache The same rule applies to all cache access stats too! --> <!-- following is AF for max power computation. Do not change them, unless you understand them--> <stat name="IFU_duty_cycle" value="0.9" /> <stat name="BR_duty_cycle" value="0.72" /><!--branch--> <stat name="LSU_duty_cycle" value="0.71" /> <stat name="MemManU_I_duty_cycle" value="0.9" /> <stat name="MemManU_D_duty_cycle" value="0.71" /> <stat name="ALU_duty_cycle" value="0.76" /> <!-- (.78*2+.71)/3 --> <stat name="MUL_duty_cycle" value="0.82" /> <stat name="FPU_duty_cycle" value="0.0" /> <stat name="ALU_cdb_duty_cycle" value="0.76" /> <stat name="MUL_cdb_duty_cycle" value="0.82" /> <stat name="FPU_cdb_duty_cycle" value="0.0" /> <param name="number_of_BPT" value="2" /> <component name="PBT"> <!-- branch predictor; tournament predictor see Alpha implementation --> <param name="local_predictor_size" value="10,3" /> <param name="local_predictor_entries" value="" /> <param name="global_predictor_entries" value="" /> <param name="global_predictor_bits" value="" /> <param name="chooser_predictor_entries" value="" /> <param name="chooser_predictor_bits" value="" /> <!-- These parameters can be combined like below in next version <param name="load_predictor" value="10,3,1024"/> <param name="global_predictor" value="4096,2"/> <param name="predictor_chooser" value="4096,2"/> --> </component> <component name="itlb"> <param name="number_entries" value="" /> <stat name="total_accesses" value="stats.system.cpu.itb.accesses" /> <stat name="total_misses" value="stats.system.cpu.itb.misses" /> <stat name="conflicts" value="0" /> <!-- there is no write requests to itlb although writes happen to itlb after miss, which is actually a replacement --> </component> <component name="icache"> <!-- there is no write requests to itlb although writes happen to it after miss, which is actually a replacement --> <param name="icache_config" value=", , ,1,1, , ,1" /> <!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy --> <!-- cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate --> <param name="buffer_sizes" value=", 4, 4, 4" /> <!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> <stat name="read_accesses" value="stat.system.cpu.icache.overall_accesses::total" /> <stat name="read_misses" value="stats.system.cpu.icache.overall_misses::total" /> <stat name="conflicts" value="0" /> </component> <component name="dtlb"> <param name="number_entries" value="" /> <stat name="total_accesses" value="stats.system.cpu.dtb.accesses" /> <stat name="total_misses" value="stats.system.cpu.dtb.misses" /> <stat name="conflicts" value="0" /> </component> <component name="dcache"> <!-- all the buffer related are optional --> <param name="dcache_config" value=", , ,1,1, , ,1" /> <param name="buffer_sizes" value=", 4, 4, 4" /> <!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> <stat name="read_accesses" value="stats.system.cpu.dcache.ReadReq_accesses::total" /> <stat name="write_accesses" value="stats.system.cpu.dcache.WriteReq_accesses::total" /> <stat name="read_misses" value="stats.system.cpu.dcache.ReadReq_misses::total" /> <stat name="write_misses" value="stats.system.cpu.dcache.WriteReq_misses::total" /> <stat name="conflicts" value="0" /> </component> <component name="BTB"> <!-- all the buffer related are optional --> <param name="BTB_config" value=",1,1,1,1,2" /> <!-- the parameters are capacity,block_width,associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,--> </component>
</component> <component name="L20"> <!-- all the buffer related are optional --> <param name="L2_config" value=",,,1,4,,,1" /> <!-- consider 4-way bank interleaving for Niagara 1 --> <!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy --> <param name="buffer_sizes" value=",16,16,16" /> <!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> <param name="clockrate" value="2000" /> <param name="ports" value="1,1,1" /> <!-- number of r, w, and rw ports --> <param name="device_type" value="1" /> <param name="vdd" value="0" /><!-- 0 means using ITRS default vdd --> <stat name="read_accesses" value="stats.system.l2.overall_accesses::total" /> <stat name="write_accesses" value="stats.system.l2.WritebackDirty_accesses::total + stats.system.l2.WritebackClean_accesses::total" /> <stat name="read_misses" value="stats.system.l2.overall_misses::total" /> <stat name="write_misses" value="stats.system.l2.WritebackDirty_accesses::total" /> <stat name="conflicts" value="0" /> <stat name="duty_cycle" value="0.2" /> </component> <component name="noc0"> <param name="clockrate" value="1000" /> <param name="vdd" value="0" /><!-- 0 means using ITRS default vdd --> <param name="type" value="1" /> <!-- 1 NoC, O bus --> <param name="horizontal_nodes" value="1" /> <param name="vertical_nodes" value="1" /> <param name="has_global_link" value="0" /> <!-- 1 has global link, 0 does not have global link --> <param name="link_throughput" value="1" /><!--w.r.t clock --> <param name="link_latency" value="1" /><!--w.r.t clock --> <!-- throughput >= latency --> <!-- Router architecture --> <param name="input_ports" value="1" /> <param name="output_ports" value="1" /> <!-- input buffer; in classic routers only input ports need buffers --> <param name="flit_bits" value="64" /> <param name="chip_coverage" value="1" /> <!-- When multiple NOC present, one NOC will cover part of the whole chip. chip_coverage <=1 --> <stat name="total_accesses" value="stats.system.mem_ctrls.num_reads::total + stats.system.mem_ctrls.num_writes::total" /> <!-- This is the number of total accesses within the whole network not for each router --> <stat name="duty_cycle" value="0.5" /> </component> <component name="mc"> <!-- Memory controllers are for DDR(2,3...) DIMMs --> <!-- current version of McPAT uses published values for base parameters of memory controller improvements on MC will be added in later versions. --> <param name="type" value="0" /> <!-- 1: low power; 0 high performance --> <param name="mc_clock" value="1000" /><!--DIMM IO bus clock rate MHz --> <param name="vdd" value="0" /><!-- 0 means using ITRS default vdd --> <param name="peak_transfer_rate" value="6400" /><!--MB/S--> <param name="block_size" value="64" /><!--B--> <param name="number_mcs" value="1" /> <!-- current McPAT only supports homogeneous memory controllers --> <param name="memory_channels_per_mc" value="1" /> <param name="number_ranks" value="2" /> <param name="withPHY" value="1" /> <!-- # of ranks of each channel--> <param name="req_window_size_per_channel" value="32" /> <param name="IO_buffer_size_per_channel" value="32" /> <param name="databus_width" value="64" /> <param name="addressbus_width" value="51" /> <!-- McPAT will add the control bus width to the address bus width automatically --> <stat name="memory_accesses" value="stats.system.mem_ctrls.num_reads::total + stats.system.mem_ctrls.num_writes::total" /> <stat name="memory_reads" value="stats.system.mem_ctrls.num_reads::total" /> <stat name="memory_writes" value="stats.system.mem_ctrls.num_writes::total" /> <!-- McPAT does not track individual mc, instead, it takes the total accesses and calculate the average power per MC or per channel. This is sufficient for most application. Further track down can be easily added in later versions. --> </component> <component name="niu"> <!-- On chip 10Gb Ethernet NIC, including XAUI Phy and MAC controller --> <!-- For a minimum IP packet size of 84B at 10Gb/s, a new packet arrives every 67.2ns. the low bound of clock rate of a 10Gb MAC is 150Mhz --> <param name="type" value="0" /> <!-- 1: low power; 0 high performance --> <param name="clockrate" value="350" /> <param name="vdd" value="0" /><!-- 0 means using ITRS default vdd --> <param name="number_units" value="0" /> <!-- unlike PCIe and memory controllers, each Ethernet controller only have one port --> <stat name="duty_cycle" value="1.0" /> <!-- achievable max load <= 1.0 --> <stat name="total_load_perc" value="0.7" /> <!-- ratio of total achieve-able load to total achieve-able bandwidth --> <!-- McPAT does not track individual nic, instead, it takes the total accesses and calculate the average power per nic or per channel. This is sufficient for most application. --> </component> <component name="pcie"> <!-- On chip PCIe controller, including Phy--> <!-- For a minimum PCIe packet size of 84B at 8Gb/s per lane (PCIe 3.0), a new packet arrives every 84ns. the low bound of clock rate of a PCIe per lane logic is 120Mhz --> <param name="type" value="0" /> <!-- 1: low power; 0 high performance --> <param name="withPHY" value="1" /> <param name="clockrate" value="350" /> <param name="vdd" value="0" /><!-- 0 means using ITRS default vdd --> <param name="number_units" value="0" /> <param name="num_channels" value="8" /> <!-- 2 ,4 ,8 ,16 ,32 --> <stat name="duty_cycle" value="1.0" /> <!-- achievable max load <= 1.0 --> <stat name="total_load_perc" value="0.7" /> <!-- Percentage of total achived load to total achivable bandwidth --> <!-- McPAT does not track individual pcie controllers, instead, it takes the total accesses and calculate the average power per pcie controller or per channel. This is sufficent for most application. --> </component> <component name="flashc"> <param name="number_flashcs" value="0" /> <param name="type" value="1" /> <!-- 1: low power; 0 high performance --> <param name="vdd" value="0" /><!-- 0 means using ITRS default vdd --> <param name="withPHY" value="1" /> <param name="peak_transfer_rate" value="200" /><!--Per controller sustainable reak rate MB/S --> <stat name="duty_cycle" value="1.0" /> <!-- achievable max load <= 1.0 --> <stat name="total_load_perc" value="0.7" /> <!-- Percentage of total achived load to total achivable bandwidth --> <!-- McPAT does not track individual flash controller, instead, it takes the total accesses and calculate the average power per fc or per channel. This is sufficent for most application --> </component> </component>
