How do I convert arrays from Verilog to VHDL?

I came across this register instantiation in a Verilog code and would like to convert this to VHDL. I understand the conversion of Instantiation 1*, but I am stuck at Instantiation 2. *Please correct me if I am wrong.

Instantiation 1:

Verilog:

reg [4:0] temp_seed [8:0];

VHDL:

type temp_seed_type (8 downto 0) of std_logic_vector(4 downto 0);
signal temp_seed : temp_seed_type;

Instantiation 2:

Verilog

reg [23:0] ola [4:0] [4:0]; 

1 Answer

You can add more dimensions in the parentheses:

type ola_type is array(4 downto 0, 4 downto 0) of std_logic_vector(23 downto 0);
signal ola : ola_type;

Reading the standard or a good beginner's book helps. ;-)