Implementing a for loop in systemverilog

I want to generate an automated input stimulus for my DUT. This input is going to different modules at the same time and working on this data. I want my input to be generated in an increasing manner. Like 0000,0001,0010,0011...1111 I tried using a for loop but it only uses the last data from the loop and works on that.

always_comb begin for (i=0, i<16; i=i+1) begin data <= i; end
end

When I give inputs individually like,

data = 8'd1;
#2;
data = 8'd2;
#2;

It works smoothly with all input values specified.

1 Answer

always_comb cannot have delays. At least per the IEEE1800 standard.

You can do something like this:

bit [3:0] data; // bit so the initial value is 0, not x
bit clk;
always #1 clk++; // or some other clock model
always_ff @(posedge clk) begin data <= data+1;
end

or something like this:

logic [3:0] data;
initial begin for (i=0, i<16; i=i+1) begin data = i; #2; end
end

Or some other similar code with time delay.